In the semiconductor processing industry, there is currently a strong trend toward scaling down existing structures and fabricating smaller structures. This process is commonly referred to as microfabrication. One area in which microfabrication has had a significant impact is in the microelectronic area. In particular, the scaling down of microelectronic structures has generally allowed the structures to be less expensive, have higher performance, exhibit reduced power consumption, and contain more components for a given dimension. Although microfabrication has been widely active in the electronics industry, it has also been applied to other applications such as biotechnology, optics, mechanical systems, sensing devices and reactors.
Microfabrication can be utilized to fabricate permanent inexpensive rugged memory (PIRM) arrays. PIRM is an extremely low cost archival solid-state memory for digital photography, digital audio and other applications. From a fabrication perspective, PIRM includes a series of semiconductor and other thin-films sandwiched between a patterned top metal layer and a patterned bottom metal layer. Where these metal layers cross forms a two-port device.
A PIRM configuration typically includes a plurality of layers whereby each layer includes a large number of memory arrays thereon. There are several reasons why it is desirable to have a large number of memory arrays on each layer of PIRM configuration. One advantage is that for a fixed minimum feature size, the larger number of arrays on each layer, the smaller each array will be. Smaller arrays consume less power since not all of the arrays need to be powered at all times. Furthermore, smaller arrays have a smaller capacitance which translates to a higher speed of operation.
Another advantage of having a large number of arrays on each layer has to do with defect management. In order for the PIRM array to obtain the low cost, the array must be tolerant of manufacturing defects. By subdividing each PIRM layer into a large number of arrays, feasible defect management strategies are facilitated whereby the amount of memory lost to an un-repairable manufacturing defect is minimized.
However, the problem with subdividing each PIRM layer into a large number of smaller arrays is the large number of connections that are required. If independent connections are made from a controller chip to each array then the number of connections needed is roughly proportional to the number of arrays. This is because the addressing has logarithmic efficiency and it takes nearly the same number of address lines regardless of the size of the array.
For example, if a 1.7 GB PIRM is divided into 12800 arrays each with independent connections to the controller chip, 371,000 connections are required. If the same 1.7 GB PIRM is divided into 128 arrays with independent connections to the controller chip, 4480 address lines are required. Neither of these examples is feasible. Not only are the number of connections to the controller die prohibitive, but layer-to-layer interconnect density and overhead routing are also unacceptably high.
Accordingly, what is needed is PIRM architecture that does not suffer from the above-delineated drawbacks of the PIRM manufacturing process. The architecture should be simple, inexpensive and capable of being easily adapted to existing technology. The present invention addresses these needs.